SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence¶

🕒 Published (v1): 2026-07-02 02:24 UTC · Source: Arxiv · link

Why this paper was selected

VLM applied to circuit schematic-to-netlist; novel EDA domain grounding task with structured output

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TL;DR¶

SINA is a fully automated pipeline that converts circuit schematic images into SPICE-compatible netlists using a four-stage architecture: YOLO-based component detection, Connected-Component Labeling (CCL) for connectivity inference, OCR for text extraction, and a VLM (GPT-4o) for reference designator assignment and netlist generation. It achieves 96.67% overall netlist accuracy, 2.72× higher than the prior state-of-the-art, and handles both IC- and PCB-level schematics including hand-drawn inputs.

Problem¶

Existing schematic-to-netlist converters fail to generalize across IC and PCB domains, mishandle crossing wires (treating non-connected intersections as junctions), produce unreliable connectivity via geometric heuristics, and cannot accurately assign reference designators when text is rotated, overlapping, or ambiguous. Manual transcription remains the dominant approach, creating a bottleneck for LLM-based EDA tools that require machine-readable circuit databases.

Method¶

SINA runs four sequential stages:

Component Detection: YOLOv11 detects components and returns bounding boxes. GPT-4o independently re-identifies components from the raw image at temperature=0; discrepancies between YOLO and GPT-4o outputs are flagged for user inspection, providing confidence scoring and out-of-distribution detection.
Connectivity Inference: Components are masked from the image; CCL segments the remaining wire traces into candidate nodes. Nodes connecting fewer than two components are pruned. A dedicated crossing-wires detection module uses morphological operations and geometric intersection analysis (restricted to perpendicular pairs) to identify non-connected crossings. For each crossing, SINA generates two modified images—each reconnecting one wire while disconnecting the other via virtual bridge components—then merges both resulting netlists to recover correct topology.
Reference Designator Extraction: EasyOCR extracts text (designators such as "R1", values such as "10kΩ") after contrast enhancement and adaptive thresholding; text is spatially mapped to nearest detected components.
Netlist Generation: GPT-4o receives the OCR text, component-to-node connectivity map, and the original image, then assigns designators/values and emits SPICE-formatted netlist lines. Structural correctness is validated via graph isomorphism between the generated netlist graph and a ground-truth reference.

For PCB-level schematics, an additional subpipeline uses OCR-guided inpainting to remove text before detection and a Skeleton OCR method (wire skeletonization + dilated bounding box intersection) for pin identification.

Key Contributions¶

Open-source schematic-to-netlist pipeline spanning IC- and PCB-level schematics, including hand-drawn and scanned inputs.
Hybrid YOLO+VLM verification: GPT-4o cross-checks YOLO detections at temperature=0, quantifying concordance as a confidence score.
CCL-based connectivity inference that avoids geometric line-tracing assumptions.
Explicit crossing-wire disambiguation via dual-image processing with virtual bridge components.
Graph isomorphism-based netlist correctness verification.
Training database covering IC/PCB schematics across simple (<6 components, 47.8%), medium (6–20, 42.1%), and complex (>20, 10.1%) categories with augmentation.

Results¶

Overall netlist generation accuracy: 96.67% vs. state-of-the-art (Masala-CHAI [8]): ~35.5% implied (2.72× improvement).
IC-level component detection: precision 93%, recall 99%, F1 96%, weighted mAP 98%.
PCB-level component detection precision: 94%.
Text (reference designator + value) extraction accuracy: 97.5%.
YOLOv11m vs. YOLOv11n: mAP 97% vs. 95%; training time 27.63 min vs. 20.52 min; inference time 39.0 min vs. 26.2 min.
Evaluated on benchmark of 75 IC-level schematics (text truncated before full PCB results reported).

Limitations¶

GPT-4o API dependency introduces cost, latency, and reproducibility concerns (temperature=0 mitigates but does not eliminate variability across API versions).
VLM used in isolation (without OCR grounding) is explicitly noted to misassign reference designators, misidentify similar components, and overlook circuit context.
Crossing-wire detection restricted to perpendicular pairs; diagonal or multi-way crossings not addressed.
Evaluation benchmark is relatively small (75 IC-level schematics explicitly mentioned); full PCB benchmark size not reported in the provided text.
Complex schematics (>20 components) represent only 10.1% of training data, potentially underrepresenting real-world dense designs.
Pin identification for PCB discrete components relies on skeleton endpoint heuristics, which may degrade under heavy occlusion.

Relevance to Vision-Language Models¶

This paper demonstrates a constrained, engineering-disciplined use of VLMs (GPT-4o) within a hybrid pipeline, illustrating that VLMs perform best as reasoners over pre-structured inputs rather than as end-to-end detectors—a pattern increasingly validated across document understanding and structured-output tasks. The explicit finding that GPT-4o alone "often struggles to accurately determine component locations and textual annotations" motivates a decomposition where neural detectors handle spatial precision while the VLM handles semantic assignment, directly informing architectures for VLM-in-the-loop pipelines. The VLM verification step—using independent model outputs for cross-checking and confidence scoring—is a transferable pattern for any VLM deployment requiring reliability guarantees. For VLM researchers, the domain (circuit schematics) also represents an underexplored structured-visual-language modality with domain-specific ontologies, offering a testbed distinct from natural-image captioning or document VQA.