AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design¶

🕒 Published (v1): 2025-12-25 10:20 UTC · Source: Arxiv · Venue: AAAI 2026 · link

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TL;DR¶

AMS-IO-Agent is a domain-specialized LLM agent that automates analog and mixed-signal (AMS) IC input/output ring design by converting natural language pin specifications into production-ready EDA schematics and layouts. It achieves >70% DRC+LVS pass rates on the new AMS-IO-Bench benchmark, reducing design turnaround from ~8 hours to ~5 minutes. An agent-generated I/O ring was fabricated and verified in a 28 nm CMOS tape-out—the first reported LLM-agent contribution directly integrated into silicon.

Problem¶

AMS IC I/O ring design is largely manual despite being repetitive: engineers must interpret informal pin specifications, apply complex domain conventions (power domains, ESD rules, multi-signal-type routing), and generate EDA scripts—work that takes a novice 1–2 days per iteration and is rarely reusable. Prior LLM-for-EDA work targets digital/RTL flows; no benchmark or agent existed for AMS I/O automation, and direct LLM code generation fails on sparse-training-data EDA DSLs (e.g., SKILL).

Method¶

AMS-IO-Agent decomposes I/O generation into three layered components:

Design Intent Structuring: Converts natural language/spreadsheet pin specs into a JSON intent graph—nodes represent pads/corners with attributes (device type, spatial position, direction, pin connections). The LLM performs explicit completion (resolving named signals via domain conventions) and implicit inference (auto-inserting corner cells). This avoids direct SKILL generation where pre-training data is scarce.
Intent Graph Adaptor: Python middleware that parses the intent graph deterministically—resolves geometric constraints, computes cell coordinates, and generates SKILL scripts for Cadence Virtuoso (schematic/layout) and csh scripts for Siemens Calibre (DRC/LVS verification). The adaptor encapsulates complex logic as a reusable tool library rather than re-generating it per run.
Domain-Specific Knowledge Base: ~6k-token in-context repository distilled from training materials of 10+ experienced AMS engineers, validated across 50+ tape-outs. Covers device selection, power domain rules, ESD requirements, naming conventions. Consumed directly by the LLM without RAG or fine-tuning.

The agent is implemented using the smolagents framework; the backbone LLM is accessed via API (GPT-4o, Claude-3.7, DeepSeek-V3 all evaluated).

Key Contributions¶

AMS-IO-Agent: First LLM-based agent targeting AMS I/O ring generation with a three-component architecture (knowledge base + intent graph + adaptor) that achieves signoff-quality outputs.
Intent graph intermediate representation: JSON-based structure capturing spatial, semantic, and electrical information—human-readable and machine-parseable, bridging informal specs and EDA toolchains.
AMS-IO-Bench: First benchmark for wirebond-packaged AMS I/O ring automation; 30 cases across three difficulty levels (simple/medium/hard), derived from 10 real tape-out projects.
Silicon validation: Agent-generated I/O ring fabricated and verified functional in 28 nm CMOS—first reported human-agent collaborative AMS IC design where the agent's output goes directly to silicon.

Results¶

AMS-IO-Bench overall (30 cases, best model Claude-3.7/DeepSeek-V3):
Intent graph pass rate: 100% (all models)
Shape score: 100% (all models)
DRC pass rate: 93.33% (Claude-3.7, DeepSeek-V3); 76.67% (GPT-4o)
LVS pass rate: 76.67% (Claude-3.7, DeepSeek-V3); 66.67% (GPT-4o)
DRC+LVS pass rate: 76.67% (Claude-3.7, DeepSeek-V3); 63.33% (GPT-4o)
Baseline LLM (GPT-4o direct): 0% on all metrics beyond intent
Design time: ~480 min (human expert) → 4–5 min (agent); token cost <200k per case
Difficulty breakdown (DRC+LVS): Simple 10/10 all models; Medium 7–10/10; Hard 2–4/10
Ablation: Removing any single component (KB, IG, or adaptor) reduces DRC+LVS to 0%; KB alone yields 20% shape but 0% DRC+LVS

Limitations¶

Benchmark is small (30 cases); may not fully cover the diversity of real-world AMS designs.
Scope limited to wirebond packaging; flip-chip and other styles require a different knowledge base and adaptor.
Knowledge base is tied to specific foundry conventions; generalizing to new technology nodes or fab rules requires manual re-curation.
Hard cases still have low pass rates (2–4/10 DRC+LVS), indicating the agent struggles with staggered pads, custom cells, and highly complex power domain configurations.
Cannot fully replace expert review; unconventional or highly customized designs still require human oversight.
Agent cannot self-correct DRC/LVS failures beyond prompt refinement; no automated feedback loop for rule violations.

Relevance to Agentic AI / LLM Agents¶

This paper is a concrete example of an LLM agent solving a real, high-stakes engineering task end-to-end—from ambiguous natural language input to verified physical artifacts—with silicon fabrication as ground truth. The key architectural insight (structured intermediate representation + deterministic middleware + compact in-context knowledge base) is a transferable pattern for any domain where LLMs have sparse pre-training data but rich expert conventions. The work also advances the human-agent collaboration paradigm: rather than full autonomy, the agent handles the repetitive layout assembly while humans review and handle edge cases, a division that proves practical at tape-out. The AMS-IO-Bench benchmark fills a gap in EDA agent evaluation, enabling future work to compare agents on complex, multi-constraint engineering tasks beyond code generation.