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VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs

🕒 Published (v1): 2026-04-16 02:30 UTC · Source: Arxiv · link

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Multi-agent hierarchical RTL generation for large hardware designs

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TL;DR

VeriGraphi is a multi-agent LLM framework for generating synthesizable hierarchical Verilog RTL directly from raw PDF specifications. It introduces a spec-anchored Knowledge Graph (KG)—the Hierarchical Design Architecture (HDA)—as a deterministic intermediate representation encoding module hierarchy, port interfaces, wiring semantics, and inter-module dependencies before any code is generated. Guided by the KG, a progressive coding pipeline incrementally generates pseudo-code and RTL bottom-up, enforcing interface consistency at each stage.

Problem

LLMs generating hierarchical Verilog from real-world PDF specifications—which contain informal text, figures, and tables—lose context across modules, hallucinate I/O ports, fabricate wiring, and fail to maintain structural coherence as design complexity grows. Prior approaches either require expert-provided decompositions, use text-centric intermediate plans that are not machine-checkable, or rely on RTL corpora rather than the original specification as the source of structural truth.

Method

VeriGraphi is a four-module pipeline:

  1. Architectural Analysis Module: A four-agent sub-pipeline (Summarizer → Decomposition → Specifier → Content Auditor) converts PDF specifications into a structured, hierarchically ordered implementation plan. The Summarizer extracts text and visual artifacts (figures/tables) using PyPDF and a custom tool; the Decomposition Agent builds a dependency-ordered module list with spec section references; the Specifier extracts per-module port/behavior descriptions; the Content Auditor drives a refinement loop checking structural completeness, bit-widths, and clarity.

  2. Hierarchy Analysis Module: A KG Builder Agent constructs the HDA—a property graph whose nodes are modules annotated with ports, widths, parameters, and spec references, and whose typed edges encode CONTAINS/INSTANCE_OF (hierarchy), DEPENDS_ON (ordering), and CONNECTS (port-to-signal wiring). The HDA is exported as JSON and a visual graph for optional human inspection.

  3. Progressive Coding Module: Five agents operate bottom-up over HDA-sorted modules (leaves first). The Pseudo Coder Agent generates structured pseudocode from the KG node and implementation plan entry. The Coder Agent translates pseudocode to synthesizable Verilog targeting iverilog -g2012. The Syntax Checker Agent validates each submodule immediately. On failure, the Prompt Enhancer Agent compresses error history—retaining only erroneous lines and messages (~80% token reduction)—and regenerates. The Code Assembler Agent constructs the top-level wrapper using INSTANCE_OF and CONNECTS edges.

  4. Verification Module: A Verifier Agent (using Claude Sonnet 4.6) derives testbenches independently from the specification—not from the generated RTL—in three steps: per-module spec summarization, module-level test case derivation (boundary conditions, spec-defined constants), and integration-level testbench construction (pipeline-depth timing, X-propagation detection).

Key Contributions

  • Spec-anchored HDA Knowledge Graph as a machine-checkable structural scaffold encoding modules, ports, signals, and hierarchical/wiring relations prior to code generation.
  • KG-guided progressive coding mechanism with bottom-up generation order, pseudo-code intermediary, and compressed error-history prompt optimization.
  • Specification-grounded verification pipeline generating testbenches from spec rather than RTL, providing independent ground truth for module-level and integration-level validation.
  • Demonstration of LLM-generated RV32I processor with minimal human intervention and HMAC with zero human intervention; fewer coding iterations than prior work.

Results

  • RISC-V 32I: Full processor generated with minimal human intervention; described as "a significant milestone for LLM-generated hardware design."
  • HMAC (NIST): Generated with zero human intervention.
  • Coding iterations: Significantly fewer than prior work, reducing generation cost.
  • Prompt Enhancer: ~80% token reduction in error-correction loop by retaining only erroneous lines and messages across iterations.
  • Evaluation covers three NIST specification documents and their reference implementations; synthesizability and functional correctness validated via Icarus Verilog simulation and PPA synthesis.

(Note: The paper text provided is truncated before detailed per-module pass rates or quantitative table data; no additional numerical baselines are reported in the available text.)

Limitations

  • Evaluation is restricted to three NIST designs plus RV32I; generalization to arbitrary industrial-scale or novel-domain specifications is unverified.
  • RV32I still requires "minimal" (non-zero) human intervention; purely autonomous generation of the most complex designs is not yet achieved.
  • The Decomposition Agent's inferred hierarchy (when specs don't define one explicitly) is only optionally reviewed by a human, leaving a potential error propagation path.
  • Verification testbenches are LLM-generated from the same spec the pipeline consumes; independent formal or hand-written golden references are not used.
  • Prompt Enhancer retry loop terminates at a fixed limit \(R\); modules that exceed \(R\) iterations are saved as unverified and require human resolution.

Relevance to Harnesses / Meta-Harnesses

VeriGraphi is a concrete instantiation of a domain-specific multi-agent meta-harness: it composes a pipeline of specialized sub-agents (Summarizer, Decomposition, Specifier, Auditor, KG Builder, Pseudo Coder, Coder, Syntax Checker, Prompt Enhancer, Code Assembler, Verifier) each with narrow responsibilities, orchestrated by shared intermediate representations (the implementation plan and the HDA Knowledge Graph). The pattern of building a machine-checkable structured artifact before downstream generation—rather than passing free-text plans—directly mirrors the "structured intermediate state" design principle seen in general-purpose agentic harnesses. The compressed error-history loop in the Prompt Enhancer is an inline self-repair harness: it manages context budget while preserving debugging signal across retries, a reusable pattern for any iterative-generation harness operating under token constraints.