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Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation

🕒 Published (v1): 2026-07-15 05:19 UTC · Source: Arxiv · link

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TL;DR

ATLAS is a three-stage, multi-agent LLM harness for end-to-end SAR ADC synthesis that constrains generation through expert-grounded RAG planning, template-constrained netlist selection, and simulation-in-the-loop debugging. It counters LLM hallucinations in analog EDA—where unconstrained prompting produces physically unviable netlists—by decomposing the design task across specialized sub-agents with rule-based verification at each boundary. The framework successfully produces functional 8-bit SAR ADCs at multiple technology nodes that pass SPICE simulation validation.

Problem

Analog EDA remains manual and intuition-driven because LLMs lack circuit topology reasoning: direct prompting produces netlists with shorted gates, wrong terminal connections, missing cross-coupling nodes, and wrong PMOS/NMOS classification (e.g., GPT-4o generates 3P/8N for a circuit requiring 7P/4N). Fine-tuned vision models fail to generalize beyond their training distribution. No prior agentic framework reliably covers full SAR ADC synthesis—existing works target simpler circuits (amplifiers, oscillators) or act as sizing-only optimizers for a fixed topology.

Method

ATLAS decomposes synthesis into three sequential stages, each orchestrated by dedicated LLM sub-agents:

Stage 1 — Grounding in Expert Knowledge. A human-curated database of open-source SAR ADC papers (derived from [41]) is summarized by an LLM into a knowledge base. A heuristic metric-proximity retriever selects the top-\(k\) closest prior circuits given the user's input specs; a Planner LLM synthesizes a high-level design plan from these summaries.

Stage 2 — Netlist Generation (two wings). Wing 1 (Grounded Zero-shot): a Generator LLM produces a component netlist guided by the plan and iterated against a rule-based verification engine (parameter matching, singular-node checks) in a fixed loop. Wing 2 (Template-Constrained, fallback): a Selector LLM chooses among curated SPICE templates (StrongArm latch, Miyahara comparator, binary-weighted and split-capacitor DAC arrays) with optional minor modifications. An Integrator LLM stitches components, a Bit-Modifier LLM adjusts bit-width, and a Testbench Creator LLM instantiates a grounded testbench template. A Debugger LLM corrects simulation errors in a SPICE-in-the-loop retry cycle.

Stage 3 — Netlist Sizing and Optimization. A Sizer LLM extracts tunable transistor/capacitor parameters, interfaced with an external multi-objective optimizer.

Key Contributions

  • Qualitative case study demonstrating that GPT-4o, Gemini 3.1, ChatGPT Plus, and multimodal/fine-tuned models all fail to generate valid SAR ADC netlists via direct prompting.
  • ATLAS: the first end-to-end multi-agent LLM harness for full SAR ADC synthesis (not just sizing).
  • Template-Constrained Generation: a component-level template selection-and-modification strategy that provides a generalized (not topology-locked) generation path while preventing free-form hallucination.
  • RAG-based expert grounding via a scientific-paper knowledge base to reduce planner hallucinations.
  • Simulation-in-the-loop Debugger LLM for automated netlist error correction.
  • Demonstrated synthesis of four SAR ADCs: 8-bit GPDK-45nm (ENOB 7.59), 8-bit TSMC-65nm, 4-bit, and 10-bit variants.

Results

  • Primary design: 8-bit SAR ADC on Cadence GPDK-45nm achieves ENOB of 7.59 and passes SPICE simulation validation end-to-end.
  • Generalization across technology nodes: same design transferred to TSMC 65nm.
  • Generalization across bit-widths: 4-bit and 10-bit SAR ADCs successfully generated.
  • Baselines (qualitative failure analysis only): GPT-4o, Gemini 3.1, ChatGPT Plus, DeepSeek-equivalent, a fine-tuned YOLO+LLM pipeline, and a GPT-4o model fine-tuned on >700 datapoints all fail to produce valid netlists reliably.
  • No quantitative head-to-head metric comparison against other agentic analog EDA systems is reported.

Limitations

  • No layout generation; all evaluation is schematic/simulation-only.
  • Template library is small and currently populated via human effort and open-source data; breadth constrains architectural diversity in Wing 2.
  • Testbench requires a human expert correction step to validate reported metrics—not fully automated.
  • Wing 1 (zero-shot generation) treated as "futuristic" and not the reliable path; reliability depends on template coverage.
  • No quantitative comparison with prior agentic analog EDA works (AnalogCoder, AmpAgent, LADAC); evaluation is proof-of-concept across four designs, not a systematic benchmark.
  • RAG retriever uses heuristic metric proximity, not semantic/structural matching.

Relevance to Harnesses / Meta-Harnesses

ATLAS is a domain-specific multi-agent harness that exemplifies several patterns central to this topic: hierarchical task decomposition into specialized sub-agents (Planner, Generator, Selector, Integrator, Bit-Modifier, Testbench Creator, Debugger, Sizer), rule-based verification gates between stages, simulation-in-the-loop retry cycles, and RAG as a grounding mechanism to constrain the generative search space. The two-wing fallback architecture—where a liberal zero-shot agent degrades to a constrained template agent on failure—is a concrete harness-level reliability pattern for high-stakes generation tasks. The paper's core finding that unconstrained LLM generation is unreliable but agent-level constraint makes it viable is a direct argument for harness-mediated agent orchestration over raw model capability.