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Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement

🕒 Published (v1): 2026-04-16 13:18 UTC · Source: Arxiv · link

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Tool-grounded self-improvement cycle for autonomous agentic RTL optimization

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TL;DR

Dr. RTL is an agentic framework for RTL hardware timing optimization that closes a loop between LLM sub-agents and industrial EDA tools (Synopsys DC + sequential equivalence checking), continuously distilling optimization trajectories into a cross-design reusable skill library. It addresses the evaluation and methodology gap in prior LLM-based RTL optimization—which used manually degraded inputs, weak open-source toolchains, and tiny designs—by operating on real human-written RTL at industrial scale.

Problem

Prior LLM-based RTL optimization benchmarks use manually degraded RTL (making the task "repair" rather than true optimization), rely on open-source synthesis tools weaker than commercial ones (so gains may not hold), and evaluate only tiny single-module designs. Methodologically, they provide only coarse design-level PPA feedback and apply pre-defined, static textbook rewriting rules that are often absorbed by modern synthesis, with no mechanism for cross-design knowledge accumulation.

Method

Dr. RTL formulates RTL optimization as a tool-grounded search over functionally equivalent RTL transformations:

\[\min_{\mathcal{D}} f(\text{WNS}, \text{TNS}, \text{Area}) \quad \text{s.t.} \quad \mathcal{D} \equiv \mathcal{D}_0\]

An orchestrator drives \(K\) rounds of iteration. Each round: 1. Timing Analysis Agent parses post-synthesis timing reports, selects top-\(k\) critical paths by slack, maps paths back to RTL regions, and diagnoses root causes (combinational depth, high fanout, control–data coupling). 2. RTL Optimization Agent generates \(N\) candidate rewrites in parallel. It first queries the skill library \(\mathcal{S}\) for matching pattern–strategy entries; if matched, applies skill-guided transformation; otherwise, conditions the LLM on timing feedback to propose a novel transformation. 3. Evaluation Agent runs commercial synthesis + sequential equivalence checking (SEC), returning (WNS, TNS, Area, SEC) with no reasoning—strict separation between execution and decision-making.

The orchestrator selects the best SEC-passing candidate via a scalar score \(\text{Score}_i = \alpha\,\text{WNS}_i^{\text{norm}} + \beta\,\text{TNS}_i^{\text{norm}} + \gamma\,\text{Area}_i^{\text{norm}} + \text{penalty}_i\) (\(\alpha=0.5, \beta=0.35, \gamma=0.15\)) and logs the full optimization trajectory as a three-layer hierarchy (round → parallel candidates → critical-path details).

Group-relative skill learning compares all \(N\) candidates from the same parent RTL using a relative advantage signal: $\(A_i = \frac{\text{score}_i - \mu_t}{\sigma_t}\)$ The Skill Learning Agent ranks candidates by \(A_i\), abstracts common structural patterns (e.g., deep decode logic, wide mux chains) and effective strategies (e.g., pre-computation, register duplication), and updates a confidence-aware skill library with occurrence count, SEC-pass count, and mean relative advantage. The current library contains 47 pattern–strategy entries.

Key Contributions

  • Realistic RTL optimization benchmark: 20 human-written Verilog designs (avg. 812 LOC, min 128, max 4615), commercial synthesis (Synopsys DC), and sequential formal equivalence checking (SEC)—~10Ă— larger than prior benchmarks
  • Multi-agent closed-loop optimization framework (orchestrator + timing analysis / RTL optimization / evaluation agents) with shared JSON state as structured inter-agent communication
  • Group-relative skill learning: converts noisy absolute PPA into stable within-group relative signals, enabling supervised-free continual self-improvement
  • Publicly released skill library of 47 pattern–strategy pairs distilled from real optimization trajectories
  • Demonstrated Pareto optimization beyond pure timing–area trade-offs under commercial synthesis

Results

  • 21% WNS improvement and 17% TNS improvement over Synopsys DC commercial synthesis baseline, across 20 human-written RTL designs
  • 6% area reduction alongside timing improvements (Pareto improvement, not a timing–area trade-off)
  • Evaluated on 20 designs spanning buffers, processors, signal-processing modules, cryptographic designs, and SoCs
  • SEC pass rate and convergence steps reported as agentic behavior metrics in addition to final PPA
  • ~10Ă— larger design scale than all compared prior works (RTLRewriter, SymRTLo, RTL-OPT, POET, CODMAS)

Limitations

  • Power excluded from optimization objective; accurate power estimation requires workload-dependent simulation
  • Only 20 designs evaluated; skill library currently limited to 47 entries
  • Requires commercial EDA tools (Synopsys DC, SEC), limiting reproducibility for open-source users
  • Microarchitecture is fixed: pipeline latency and macro-level structure must be preserved
  • Group-relative advantage signal is heuristic and design-dependent; noisy EDA outcomes may still distort skill confidence over sparse data
  • No LLM fine-tuning loop; optimization quality depends on base model generalization to RTL idioms

Relevance to Harnesses / Meta-Harnesses

Dr. RTL is an archetypal domain-specific agentic harness: it wires together specialized sub-agents (analysis, optimization, evaluation) in a deterministic orchestration loop with external tool calls (EDA synthesis + formal verification) as grounding, using a shared structured JSON state as the inter-agent communication bus—a direct instantiation of the orchestrator-plus-specialists harness pattern. The group-relative skill learning mechanism elevates it to a meta-harness: the framework introspects its own optimization trajectories to improve the internal strategy library that guides future agent behavior, achieving test-time self-improvement without parameter updates. The hierarchical trajectory representation (round → group → critical-path) is a concrete design for harness-level memory that tracks not just outcomes but structured reasoning context, directly applicable to any harness seeking to accumulate reusable cross-task knowledge. This provides a worked example of how a harness can close the loop between tool-grounded execution and learnable, human-interpretable policy distillation.