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AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting

🕒 Published (v1): 2026-06-16 03:22 UTC · Source: Arxiv · link

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TL;DR

AUTOGATE is an agentic framework for workload-aware fine-grain clock gating (FGCG) in industrial-scale RTL designs, combining ML-based waveform clustering with LLM-guided RTL rewriting. An orchestrator decomposes hierarchical designs into modules, per-module rewrite agents apply four RTL transformation templates guided by compact clustering reports, and a reflection agent accumulates rewrite lessons across iterations. It achieves 49.31% average dynamic power reduction on small benchmarks and 19.34% / 7.96% on NVDLA / BlackParrot, where prior single-agent methods fail to improve.

Problem

Two fundamental blockers prevent LLM-based RTL optimization from scaling to industrial FGCG: (1) cycle-accurate toggling traces span millions of clock edges — far beyond LLM context limits — so workload-dependent gating opportunities cannot be reasoned about directly; (2) prior LLM RTL optimization targets small single-module designs (\(\lesssim\)hundreds of lines), whereas production designs (NVDLA: 135 files, \(\sim\)1.0M tokens; BlackParrot: 77 files, 30.6M tokens) have deep cross-module hierarchies that a single-agent, single-context approach cannot navigate. Commercial synthesis infers FGCG only from RTL coding style, missing workload-dependent opportunities that require RTL restructuring.

Method

AUTOGATE operates as a four-stage ML–LLM co-design pipeline:

Stage 1 — Hierarchy detection and pre-profiling. An orchestrator parses module definitions and instantiations into a parent–child tree, performs one full-design synthesis and power analysis, maps gate-level power back to source RTL regions, and ranks modules by optimization value. Module-level testbenches for bottleneck modules are extracted by scoping full-design simulation waveforms (no synthetic stimuli), enabling accurate per-module switching traces while avoiding re-simulation.

Stage 2 — Adaptive stability-based FGCG exploration. Raw switching traces are compressed into binary stability patterns \(\text{SP}_a \in \{0,1\}^T\), where \(\text{SP}_a[k]=1\) if register \(a\) is unchanged at clock edge \(k\). Group gating efficiency is \(E(G) = \frac{1}{T}\sum_{k=1}^{T}\bigwedge_{a \in G}\text{SP}_a[k]\). Three sub-steps: (1) toggle-aware pre-filter excludes registers with Q/CLK ratio \(<3\%\) or \(>95\%\); (2) automatic threshold discovery evaluates the efficiency spectrum \(\mathcal{E}_b = \{E(H)\mid H\subseteq R,|H|=b\}\) for minimum group width \(b=4\), identifies largest consecutive gaps, and uses gap midpoints as candidate \(\text{minE}\) values — replacing manual tuning; (3) agglomerative stability-based clustering merges closest pairs \(C_i, C_j\) under \(d(C_i,C_j)=\|\text{SP}_{C_i}-\text{SP}_{C_j}\|_2\), accepting merges only when \(E(M)\geq\text{minE}\). Multi-threshold clustering sweeps all detected \(\text{minE}\) values to produce a candidate hierarchy spanning fine/medium/coarse granularity.

Stage 3 — LLM-guided parallel rewriting. Modules are scheduled bottom-up; leaf modules are optimized first, sibling modules in parallel. Each module gets a dedicated rewrite agent operating only on its RTL, guided by its power-bottleneck report and clustering candidates. Agents apply four templates: (1) enable/hold extraction, (2) value-change-based gating, (3) control-signal factoring, (4) register decomposition. A reflection agent evaluates variants, diagnoses regressions, and distills lessons into module-specific and global playbooks shared across agents.

Stage 4 — Formal verification and QoR-aware merge. Each candidate undergoes syntax checking, simulation, commercial formal equivalence checking, and timing closure. Survivors are synthesized for QoR profiles (\(\Delta P_\text{dyn}\), \(\Delta A\), clock-gating coverage/efficiency, ICG count, WNS, TNS). The best power-reduction candidate satisfying area and timing constraints is selected; accepted patches are merged hierarchically and revalidated at parent level.

Key Contributions

  • First agentic framework for industrial-grade RTL power optimization, scaling to multi-million-line hierarchical designs
  • ML–LLM co-design that distills million-cycle waveform traces into compact, structured clustering reports consumable by LLMs — eliminating the long-context bottleneck
  • Automatic FGCG threshold discovery via group-wise efficiency spectrum, removing the fragile manual \(\text{minE}\) parameter
  • Divide-and-conquer hierarchical multi-agent orchestration with bottom-up scheduling and shared reflection playbooks
  • Formal equivalence verification integrated into the optimization loop, guaranteeing functional correctness at each merge

Results

  • Small benchmarks (6 designs, CVDP/OpenCores/OpenTitan): 49.31% average dynamic power reduction, 0.15% average area overhead, all timing constraints met
  • NVDLA (135 files, 1.0M tokens): 19.34% dynamic power reduction, 3.46% average area reduction across partitions vs. POET (+0.09%) and ROVER (−0.01%)
  • BlackParrot (77 files, 30.6M tokens): 7.96% dynamic power reduction, 0.04% area overhead
  • Proprietary production designs: up to 6.86% dynamic power reduction, \(\leq\)1% area overhead on highly optimized designs
  • booth_mult: −86.21% dynamic power vs. −85.52% (POET) and −79.72% (ROVER); AUTOGATE extends these gains to the full hierarchical NVDLA where prior methods stall
  • Clock-gating coverage and efficiency improve on all reported designs; timing closure preserved across all experiments

Limitations

  • Toggle-rate pre-filter thresholds (3% / 95%) and minimum group bit-width (\(b=4\)) are fixed heuristics not systematically tuned
  • Workload generalization is not evaluated — results are tied to the specific simulation workload used to extract traces
  • Requires commercial formal equivalence and timing analysis tools, limiting accessibility
  • Full-design synthesis and power analysis required once upfront — expensive for very large SoCs
  • Multi-threshold clustering samples candidate groups for large register sets; the sampling strategy may miss optimal thresholds in some distributions

Relevance to Harnesses / Meta-Harnesses

AUTOGATE is a concrete instantiation of the multi-agent meta-harness pattern in the EDA domain: an orchestrator agent performs global planning (hierarchy parsing, module ranking, work scheduling), spawns specialized sub-agents per module, and a reflection agent writes cross-agent shared memory (playbooks) that feeds back into subsequent iterations. The Stage 2 ML pre-processing stage is a textbook harness "context compression" primitive — transforming intractably long raw inputs (million-cycle traces) into structured, LLM-consumable representations, which is directly analogous to chunking/summarization stages seen in document-processing and code-analysis harnesses. The bottom-up scheduling of module agents with parent-level revalidation mirrors DAG-based pipeline harnesses with dependency ordering. For researchers tracking harness design patterns, this paper offers a worked example of integrating non-LLM ML preprocessing, hierarchical task decomposition, persistent cross-agent memory, and formal verification gates as composable pipeline stages.